/*
 * LoRa.h
 *
 *  Created on: May 30, 2020
 *      Author: admin
 */

#ifndef INC_LORA_H_
#define INC_LORA_H_

#include "main.h"
#include "spi.h"
#include "gpio.h"
#include "usart.h"
#include "stm32f4xx_it.h"

//#define LoRa_Callback

// registers
#define REG_FIFO                        0x00
#define REG_OP_MODE                     0x01
#define REG_FRF_MSB                     0x06
#define REG_FRF_MID                     0x07
#define REG_FRF_LSB                     0x08
#define REG_PA_CONFIG                   0x09
#define REG_LR_OCP                      0X0b
#define REG_LNA                         0x0c
#define REG_FIFO_ADDR_PTR               0x0d
#define REG_FIFO_TX_BASE_ADDR           0x0e
#define REG_FIFO_RX_BASE_ADDR           0x0f
#define REG_FIFO_RX_CURRENT_ADDR        0x10
#define REG_IRQ_FLAGS                   0x12
#define REG_RX_NB_BYTES                 0x13
#define REG_PKT_RSSI_VALUE              0x1a
#define REG_PKT_SNR_VALUE               0x1b
#define REG_MODEM_CONFIG_1              0x1d
#define REG_MODEM_CONFIG_2              0x1e
#define REG_PREAMBLE_MSB                0x20
#define REG_PREAMBLE_LSB                0x21
#define REG_PAYLOAD_LENGTH              0x22
#define REG_MODEM_CONFIG_3              0x26
#define REG_RSSI_WIDEBAND               0x2c
#define REG_DETECTION_OPTIMIZE          0x31
#define REG_DETECTION_THRESHOLD         0x37
#define REG_SYNC_WORD                   0x39
#define REG_DIO_MAPPING_1               0x40
#define REG_VERSION                     0x42
#define REG_PaDac                       0x4d//add REG_PaDac

// modes
#define MODE_LONG_RANGE_MODE            0x80
#define MODE_SLEEP                      0x00
#define MODE_STDBY                      0x01
#define MODE_TX                         0x03
#define MODE_RX_CONTINUOUS              0x05
#define MODE_RX_SINGLE                  0x06

// PA config
#define PA_BOOST                        0x80
#define RFO                             0x70

// IRQ masks
#define IRQ_TX_DONE_MASK                0x08
#define IRQ_PAYLOAD_CRC_ERROR_MASK      0x20
#define IRQ_RX_DONE_MASK                0x40

#define MAX_PKT_LENGTH                  255

#define PA_OUTPUT_PA_BOOST_PIN          1
#define PA_OUTPUT_RFO_PIN               0

#define IMPLICIT_HEADER_MODE		1
#define EXPLICIT_HEADER_MODE		0

typedef struct {
  uint32_t      frequency;
  uint8_t       txPower;
  uint8_t       packetIndex;
  uint8_t       syncCode;
  uint8_t       spreadingFactor;
  uint8_t       codingRate;
  uint32_t      signalBandwidth;
  uint8_t       implicitHeaderMode;
} LoRaAttr_t;

uint8_t LoRa_ReadRegister(uint8_t address);
void LoRa_WriteRegister(uint8_t address, uint8_t value);
int LoRa_Init(LoRaAttr_t* LoRaAttr);
void LoRa_LowDataRateOptimize(uint8_t status);
void LoRa_End();
void LoRa_BeginPacket(uint8_t implicitHeader);
void LoRa_EndPacket();
uint8_t LoRa_ParsePacket(uint8_t headerMode);
uint8_t LoRa_PacketRssi();
uint8_t LoRa_PacketSnr();
uint8_t LoRa_WriteFifoByte(uint8_t data);
uint8_t LoRa_WriteFifoBytes(const uint8_t *buffer, uint8_t size);
uint8_t LoRa_Available();
uint8_t LoRa_ReadFifo();
uint8_t LoRa_Peek();
void LoRa_Receive(uint8_t size);
void LoRa_Idle();
void LoRa_Sleep();
void LoRa_SetTxPower(uint8_t level, uint8_t outputPin);
void LoRa_SetTxPowerMax(uint8_t level);
void LoRa_SetFrequency(uint32_t frequency);
void LoRa_SetSpreadingFactor(uint8_t sf);
void LoRa_SetSignalBandwidth(uint32_t sbw);
void LoRa_SetCodingRate(uint8_t denominator);
void LoRa_SetPreambleLength(uint16_t length);
void LoRa_SetSyncWord(uint8_t sw);
void LoRa_EnableCrc();
void LoRa_DisableCrc();
uint8_t LoRa_Random();
void LoRa_DumpRegisters();
void LoRa_ExplicitHeaderMode();
void LoRa_ImplicitHeaderMode();
void LoRa_HandleDio0Rise();
void LoRa_HandleDio1Rise();
void OnReceiveCallback(uint8_t packetLength);

#endif /* INC_LORA_H_ */
